<Data center>Senior Design Engineer - Die-to-Die Interface
Core
Develop Die-to-die and UCIe digital IP for High-Performance Computing (HPC) System-on-Chip (SOC) and integrate controllers with PHYs.
Role type
Senior IC digital design engineer (Die-to-Die Interface)
Builds
Digital IP blocks for HPC SoCs
Domain
Semiconductor design, High-Performance Computing
Deliverable
production ML models | product features | infrastructure
Required skills
Die-to-die interface design, UCIe protocol knowledge, digital IP development, timing closure, DFT integration
Preferred skills
Mixed-mode design collaboration, firmware integration
Technologies
UCIe, D2D controllers, PHYs
Responsibilities
Develop Die-to-die and UCIe digital IP for HPC SOC, Integrate D2D controller and PHY to timing closure and DFT, Define interface specifications and create verification plans, Collaborate with mixed-mode designers and firmware engineers
Seniority
Senior, hands-on IC
