Senior Hardware ASIC Arch/Design Engineer
Core
Define architecture for compute, memory, interconnect, and high-speed interface subsystems in AI inference chips, leading PPA analysis and HW-SW co-design for real-world AI workloads.
Role type
Senior IC hardware ASIC architecture engineer (AI inference)
Builds
AI inference chips
Domain
Semiconductor / AI hardware
Deliverable
production ML models
Required skills
AI inference workloads, dataflows, quantization, memory bandwidth optimization, PPA analysis, RTL implementation guidance, interface specification, pipeline structures, simulation and architectural modeling
Preferred skills
Edge deployment experience, software scalability planning
Technologies
RTL, emulation, simulation tools
Responsibilities
Define product feature and capabilities for compute, memory, interconnect & high-speed interface subsystems; Collaborate with software teams to co-optimize hardware features for AI workloads; Review and guide RTL implementation ensuring consistency with architectural intent; Lead PPA analysis and trade-off discussions; Develop and maintain high-level architecture and performance models; Validate model predictions against RTL or emulation results
