Physical Design Engineer - Foundry Team
Core
Physical design and timing closure for complex System-on-Chip (SoC) top-level implementations in mobile application processors, modem sub-systems, and connectivity chips.
Role type
Senior Physical Design Engineer (Foundry Team)
Builds
Next-generation SoCs for mobile and connectivity applications
Domain
Semiconductor / VLSI Design / Foundry
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design (Synthesis, Place and Route, STA), Timing closure, Floor planning, PPA optimization, Scripting (Perl/Tcl), LVS/DRC verification, Deep sub-micron design knowledge (8nm/5nm), SOC tape-out experience
Preferred skills
Top-level floor planning, High-speed signal and clock planning, Low power checking, Logic equivalence checking, Mixed signal block integration
Technologies
ICC, DC, PT, VSLP, Redhawk, Calibre, Formality
Responsibilities
Perform complex SOC top physical implementation; Execute timing and physical signoffs; Optimize PPA trade-offs; Debug LVS/DRC issues at chip/block level
Seniority
Senior, hands-on IC
