Engineer/Staff Engineer – Chip Physical Verification Engineer
Core
Define and enable physical sign-off flow and solutions for System-on-Chip (SOC) design in advanced technology nodes.
Role type
Staff Engineer, Chip Physical Verification
Builds
Tape-out ready SOC designs
Domain
Semiconductor / Chip Design / Physical Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full-chip Physical Verification Sign-off, DRC, LVS, ANT, ERC, ESD, PERC, Layout integration, IP coordination, Manufacturing DRC coordination, Automation solutions
Responsibilities
Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out; Co-work with Place & Route team to resolve full-chip layout integration issues; Coordinates with internal IP owners on IP related issues; Coordinates with Manufacturing Team on DRC related issues; Provide automation solutions to improve efficiency in tape-out flow; Report on tapeout PV issues.
Seniority
Staff, hands-on IC
