DFT STA Lead
Core
End-to-end DFT STA including SDC creation, sanity checks, CCD, CTS cleanup, and all-mode timing closure for top and block levels.
Role type
DFT STA Lead
Builds
Digital chips with timing closure
Domain
Semiconductor / Digital Design
Required skills
SDC creation, timing closure, CCD, CTS analysis, block-level design, top-level design
Preferred skills
Team leadership, quality execution
Technologies
SDC, CCD, CTS
Responsibilities
Create SDC in all modes, perform SDC sanity checks, execute CCD, clean up DFT CTS, achieve all-mode timing closure, lead DFT STA team
Seniority
Lead, hands-on IC
