NAND BM IP RTL Design Engineer
Core
Designing high-performance RTL for Samsung Memory products (Flash, DRAM) with a focus on concept study, specification, and micro-architecture.
Role type
Senior IC RTL Design Engineer (Memory)
Builds
Memory IP blocks (Flash, DRAM) for System LSI and Storage Solutions
Domain
Semiconductor / Memory / RTL Design
Deliverable
production ML models | product features
Required skills
Verilog, System Verilog, complex state machine design, data path design, arbitration logic, emulation-compatible RTL design, unit-level testbench creation, performance simulation, area optimization, FPGA prototyping, micro-architecture documentation
Preferred skills
Memory design experience, area optimization on emulation platforms
Technologies
Verilog, System Verilog, FPGA
Responsibilities
Perform concept and specification study for Samsung Memory (Flash, DRAM), provide high-quality RTL design optimized for performance and area, write detailed design specification and micro-architecture documents, model and simulate performance, develop FPGA-based prototypes
Seniority
Senior, hands-on IC
