ASIC Physical Design
1,421 open positions
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<Automotive>Senior Automotive SoC System Architect or Manager MediaTekHsinChu 5mo Lead architectural domains for SoC design and product technical feasibility studies, focusing on system performance and power for automotive applications.
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Senior Physical Design Leader MCU NxpYokneam Ilit 5mo Lead physical design activities for complex SoC architecture development within NXP's MCU business.
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Logic Design Engineer CiscoCaesarea, Israel 5mo Designing micro-architecture and RTL for large-scale programmable silicon devices that power Cisco's future routing portfolio.
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Quantitative Technologist (Full-Time - FPGA Engineer, PhD) RadixuniversityRadix Trading Chicago 5mo Design and build scalable FPGA systems to improve performance and latency for automated trading.
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Principal Engineer - Hardware Sustaining HpeSingapore, Central Singapore, Singapore 5mo Lead hardware failure analysis and drive root cause/corrective actions for HPE networking products to ensure best-in-class customer experience.
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UCIe Applications Engineering Architect↗ SynopsysSunnyvale, CA, US $184k–$184k5mo Provide technical leadership and expert guidance for deploying Synopsys UCIe IP in complex ASIC/SoC designs, addressing integration challenges across the customer deployment lifecycle.
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Physical Design Intern MarvellCordoba, Argentina 5mo Implement tool flows, develop CAD methodologies, and generate scripts for ASIC physical design tasks including place and route, timing closure, and backend activities.
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Staff Digital Engineer SemtechIND - Hyderabad 5mo Define, develop, verify, and optimize complex digital circuits for low-power mixed-signal ICs, collaborating on system specifications and supporting silicon evaluation.
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Senior Staff Engineer, Digital Design Renesas-ElectronicsBengaluru, KA, in 5mo Design of optimized digital blocks meeting functional, cost, and low power constraints for mixed-signal integrated circuits.
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Senior FPGA IP Solution Design Engineer AlteraPenang 15, Penang, Malaysia 5mo Designing, developing, and verifying wireless IP cores for FPGA platforms to deliver high-performance wireless solutions.
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Senior Principal System Technologist ArmCambridge, United Kingdom 5mo Designing and developing systems architecture for future semiconductor products, focusing on performance modeling, trade-offs, and IP integration.
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Senior ASIC Design Engineer - NOC IP NVIDIAIndia, Bengaluru 5mo Designing micro-architecture and RTL for memory subsystem components in Graphics Processors.
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CPU power Architect IntelIsrael, Haifa 5mo Define next-generation CPU power management architecture and deliver architectural specifications for Intel Architecture group.
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FPGA Design Engineer - Poland Arista-NetworksPoland - Remote, pl 5mo Design, implement, verify, and test FPGA-based digital systems for cutting-edge networking products.
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Workload / Performance Model Lead SifiveSanta Clara, California, United States $231k–$231k5mo Lead benchmarking and performance infrastructure development for RISC-V CPU IPs and accelerators.
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Physical Design Engineer Enchargeai36India 5mo Drive RTL-to-GDSII implementation and physical design closure for next-generation in-memory computing chips.
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FPGA - Specialist/Tech lead AfryPune, MH, in 5mo Developing FPGA code and designs for product development and IT operations, focusing on domain crossing, timing analysis, and floorplanning.
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Sr. FPGA /CPLD Engineer (Server & Storage-三重) JabilSanchong 5mo Develop server and storage power-on sequence control logic and subsystem architectures using CPLD/FPGA designs.
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Senior Staff Power Performance Architect Accelerator Design d-MatrixSanta Clara 5mo Pre-silicon power estimation and performance optimization for AI accelerator blocks using RTL and physical design analysis.
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SOC Physical Design and STA Methodology Engineer Samsung ElectronicsSSIR, Goldstone, Bangalore, India 5mo Develop production-grade PnR and STA signoff flows, automation utilities, and methodology best practices for SoC physical design at advanced nodes.
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