Computing System Architecture Engineer (Memory System Model and Optimization)
Core
Designing memory subsystems and interconnects for smartphones, automotive, HPC, and data centers, with a focus on system-level SW/HW behavioral power/performance analysis and optimization.
Role type
Senior IC computing system architecture engineer (memory system model and optimization)
Builds
Memory controllers, system caches, on-chip and cross-chip interconnects
Domain
Semiconductor hardware architecture, high-performance computing, automotive, data center
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Memory subsystem architecture, interconnect design, system-level SW/HW behavioral analysis, power/performance optimization, memory profiling, modeling, competitive analysis
Responsibilities
Design memory subsystems and interconnects for various platforms; Perform system-level SW/HW behavioral power/performance analysis; Conduct memory subsystem performance/power profiling, modeling, and competitive analysis
Seniority
Senior, hands-on IC
