Digital Design Engineer Lead (DDR5 SPD Hub)
Core
Lead the design development, implementation, and verification of digital logic for DDR5 SPD Hub (Serial Presence Detect Hub) including register interface, control logic, security features, and I3C/I²C communication modules.
Role type
Senior IC digital design engineer lead (DDR5 memory subsystem)
Builds
DDR5 SPD Hub chips for memory systems
Domain
Semiconductor / Memory Subsystems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL development (Verilog/SystemVerilog), digital design verification (UVM), ASIC development process, memory subsystem architecture, I3C/I²C protocol knowledge, security logic implementation, scripting/automation (Perl/TCL/Python/C++)
Preferred skills
DDR4/DDR5 or SPD/RCD device experience, embedded designs/firmware development, mixed signal design, power management industry applications
Technologies
Verilog, SystemVerilog, UVM, Perl, TCL, Python, C++, C++, I3C, I²C, SMBus, EEPROM
Responsibilities
Define micro-architecture for DDR5 SPD Hub features; Develop and lead RTL for control logic, ECC/parity, and protection mechanisms; Lead digital design verification and testcase creation; Collaborate with analog/mixed-signal, DFT, and physical design teams for full-chip integration; Work with firmware and validation teams for system-level behavior; Participate in bring-up, validation, and failure analysis for engineering samples; Provide design specs, timing diagrams, and integration guides
Seniority
Senior, hands-on IC with leadership
