Senior ASIC Design Engineer
Core
Designing wireless MAC controllers and system-level development for next-generation IoT connectivity chips.
Role type
Senior ASIC Design Engineer
Builds
Secure tri-radio devices for IoT connectivity
Domain
Semiconductor / Wireless Connectivity
Deliverable
production ML models | product features
Required skills
Micro-architecture design, Verilog RTL coding, IP/SoC verification, C/C++, System Verilog, UVM, FPGA prototyping, silicon bring-up, low power design, SOC integration
Preferred skills
Bluetooth, IEEE 802.15.4, HW/SW co-simulation, synthesis, Lint/CDC, formal verification, SVA assertion, coverage driven verification, Perl, Python, shell script, Tcl
Technologies
System Verilog, UVM, C/C++, Perl, Python, Tcl, FPGA
Responsibilities
Full ASIC design cycle from micro architecture to silicon bring-up, IP/SoC verification in C/C++ and System Verilog, solving complex design and verification problems
Seniority
Senior, hands-on IC
