ASIC Physical Design
1,421 open positions
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RTL Design for Data Center Chassis MediaTekSan Jose, CA 9mo Architecting, adopting, and designing chip/chiplet chassis building blocks for data center silicon.
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Principal Real Time Interconnect Architect ArmMultiple locations 9mo Lead the definition and demonstration of Quality of Service (QoS) capabilities across Arm's IP portfolio and systems to ensure real-time predictability, power management, and performance.
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Semiconductor Digital Architect, Texas Institute for Electronics UtaustinAUSTIN, TX, US 10mo Develop next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems, enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms.
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Staff Logic Design Engineer FlirUS - Milpitas, CA $142k–$142k10mo Architect and implement high-performance digital logic for protocol capture, analysis, and emulation in FPGA-based systems.
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Senior RTL Design Engineer CiscoArmenia 10mo Senior RTL Design Engineer driving next-generation silicon architecture development, defining Physical Design methodologies, and leading sub-system/SoC integration for advanced ASICs.
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Lead RTL Design Engineer CerebrasHeadquarters/Sunnyvale Office $175k–$175k10mo Lead RTL design engineer developing the Cerebras Wafer Scale Engine (WSE) architecture for high-performance AI training and inference.
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Lead Architect, Custom Silicon GlobalFoundriesUSA - Texas - Richardson $132k–$132k10mo Define and drive the architecture of next-generation custom silicon solutions, including complex ASICs and SoCs, from concept through tape-out.
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SOC IP RTL Development Engineer Samsung Electronics 11mo Designing high-speed serial interface IP blocks for System LSI and Mobile SoCs.
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Sr Principal Design Engineer CadenceBANGALORE 1y Design, implement, and verify RTL for PCIe controllers and related subsystems, ensuring protocol compliance and performance targets.
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Research Associate (IC Design) NtuNTU Main Campus, Singapore 1y Integrate Hardware AES and ASCON accelerators into the RISC-V CVA6 core, including custom instruction definition, toolchain modification, and verification.
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Senior Chip Design Engineer NVIDIAIsrael, Tel Aviv 1y Design and implement next-generation high-speed Switch Silicon chips, focusing on RTL units and blocks to deliver high throughput and low latency.
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Sr. Staff Digital DE MonolithicpowerChengdu - China 1y Leads end-to-end design and development of digital and mixed-signal ICs for power management, signal management, and mixed-signal functions.
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Physical Design Engineer EtchedSan Jose 1y Own block-level implementation and verification, drive timing closure and PPA optimization for ASIC infrastructure focused on inference workloads.
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Senior FPGA Design/Verification Engineer LumentumCanada - Ottawa (Bill Leathem) 1y Design and verify control and datapath logic for next-generation optical switches and amplifiers in high-speed data transmission systems.
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Principal Engineer, Performance Modelling Renesas-ElectronicsRemote 1y Develop and maintain performance models for System-on-Chip (SoC) designs using Platform Architect or Emulation Platform to optimize performance and ensure successful product delivery.
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STA methodology engineer NxpBangalore 1y Benchmark logic libraries across advanced technology nodes (40nm to 5nm) using synthesis and PNR flows to ensure robust STA methodologies for real-world chips and blocks.
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