Sr Principal ASIC / RTL Design Engineer
Core
Senior Principal Digital Design Engineer developing power management products (DC-DC PMIC, controllers, SiC drivers) for consumer, industrial, and automotive applications.
Role type
Senior Principal IC Design Engineer (Digital/RTL)
Builds
Power management ICs (PMICs), multiphase controllers, SiC drivers, and related digital IPs
Domain
Semiconductor / Power Management / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital RTL design, ASIC synthesis, timing analysis, CDC (Clock Domain Crossing), P&R, UPF, System Verilog assertions, Verilog, TCL, Perl/Python/XML programming, Micro-architecture implementation, Platform-based development, Digital architecture trade-offs (PPA), End-to-end digital design flow
Preferred skills
Experience with microprocessor interconnects, Integrating peripherals into interconnects, Methodology development
Technologies
RTL2GDS flows, State of the art RTL design tools, System Verilog, Verilog, TCL, Perl, Python, XML
Responsibilities
Perform trade-off analysis between different architecture options, Perform benchmarking of platform components, Define and deploy platform front end tool flow, Implement micro-architecture to RTL implementation, Work with methodology development teams to establish development methods and coding processes, Collaborate with design architects, verification, and analog design teams
Seniority
Senior Principal, hands-on IC design with leadership responsibilities