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Hardware & Physical Engineering
› ASIC Physical Design
ASIC Physical Design
1,425 open positions
Experienced SoC Design Engineer
Arm
Manchester, United Kingdom
5mo
Designing and integrating subsystems and logic for sophisticated processing systems optimized for performance and power across IoT, Automotive, and Infrastructure computing.
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Staff Digital Design Engineer
ON Semiconductor
Cork, Co. Cork, Ireland
5mo
Architecting and implementing digital FSM-based controllers and digital-on-top subsystems for mixed-signal and power management solutions.
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Neural Processing Unit Digital Designer
MediaTek
HsinChu
5mo
Designing, developing, and optimizing the architecture of neural processing units (NPUs) to meet performance, scalability, and efficiency requirements.
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Senior Principal System Performance Architect
Arm
Austin, Texas
$309k–$309k
6mo
Define SoC system and subsystem use-case performance and analysis requirements, driving analysis and testing from models to RTL to craft future compute infrastructure performance.
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interconnect fabric design and system level cache IP engineer
MediaTek
HsinChu
6mo
Design interconnect, fabric, and system-level cache IP for products including smartphones and automotive.
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Lead STA Engineer
Texas Instruments
Bengaluru, Karnataka, India
6mo
Drive timing closure and synthesis optimization for advanced connectivity SoCs to ensure wireless solutions meet performance, power, and area requirements.
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HSI Digital IC Design Engineer
MediaTek
HsinChu
6mo
Design and integrate high-speed interface subsystems (PCIe, USB, MIPI, HDMI, DisplayPort, CSI) and develop security and Functional Safety (FuSa) functions for digital circuits.
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<Data Center>Serdes Digital IC Design Engineer
MediaTek
HsinChu
6mo
Design and deliver ASIC Serdes PHY architecture for data center and AI products, focusing on low power, cost-effective, and high-speed performance.
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SoC Integration IC Design Engineer
MediaTek
HsinChu
6mo
Integration of flagship smartphone and automotive System-on-Chip (SoC) designs, including floorplan and clock architecture.
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Memory Controller Digital Engineer
MediaTek
HsinChu
6mo
Designing memory system architecture and developing DRAM controller IP for System on Chip (SoC) applications.
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Senior/Expert Hardware Design Engineer - FPGA
Sopra-Steria
Montréal, QC, ca
6mo
Design, develop, and validate complex electronic modules (FPGA, CPLD, electronic boards, ASIC) for automotive and avionics applications, focusing on video processing and 4K resolution pipelines.
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Staff Digital IC Design Engineer
Renesas-Electronics
Lviv, ua
6mo
Design and integrate digital sub-blocks and chip-level implementations, performing verification, DFT strategy, and tape-out preparation for embedded semiconductor solutions.
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RTL Design Engineer
Etchedai
Hardware Engineering
6mo
Develop and implement design verification strategies for AI chips (ASICs) optimized for specific model architectures like transformers.
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Electrical Engineer, Hardware Systems
Etchedai
Hardware Engineering
6mo
Designing schematic layouts for AI accelerator mezzanine cards and base boards to enable high-throughput, low-latency inference for transformer-based models.
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Performance Modeling Engineer
Etchedai
Hardware Engineering
6mo
Develop and own SoC functional models for Etched's Sohu ASIC (transformer-optimized) from architecture to deployment, ensuring performance alignment with AI workloads.
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Physical Design Engineer
Etchedai
Hardware Engineering
6mo
Implement and verify physical designs for AI chips (ASICs) optimized for specific model architectures like transformers.
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Reliability Engineer
Etchedai
Hardware Engineering
6mo
Ensuring components and systems meet rigorous reliability standards for datacenter applications and AI chips.
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ASIC Timing Engineer
Etchedai
Hardware Engineering
6mo
Driving timing analysis and closure for next-generation AI chips designed for specific model architectures.
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Power Optimization Engineer
Etchedai
Hardware Engineering
6mo
Develop chip power models, estimate power from microarchitecture, and devise power-saving techniques for AI ASICs.
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CPU Performance Architect
Intel
US, Texas, Austin
$142k–$232k
6mo
Design and develop CPU logic, defining architecture and microarchitecture features to optimize power, performance, and area for Intel's silicon products.
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CPU Physical Design Engineer
MediaTek
Singapore
6mo
Physical design and development of MediaTek's GHz ARM-based microprocessors, focusing on timing-critical partition blocks.
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Principal SoC RTL Engineer
Ambiqmicroinc
Austin HQ
6mo
Own pre-tapeout quality for digital SoC modules on MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon.
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Computing System Architecture Engineer (System Analysis and Model)
MediaTek
HsinChu
6mo
Conducting R&D on computing system architecture and performing system-level software/hardware behavior performance and power modeling for SoC optimization.
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Neural Processing Unit Design Engineer
MediaTek
HsinChu
6mo
Designing the architecture and RTL for AI processor subsystems, focusing on performance, power, bandwidth, and area optimization.
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Staff Digital Design Engineer
Semtech
CHE - Neuchatel
6mo
Leading the design and development of digital subsystems within complex mixed-signal ICs, from initial concept through to lab validation.
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Architect MTS
ON Semiconductor
Bangalore, Karnataka, India
6mo
Define the design architecture and methodologies for a new platform of digital compute and analog/mixed-signal products, targeting a large variety of different products.
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Principal Design Engineer
Cadence
GYEONGGI-DO (Seoul)
6mo
Lead physical design implementation projects for low power and high speed ASICs at deep sub-micron nodes, including floor planning, P&R, timing closure, and signoff.
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Staff RTL Design Engineer
Arm
Austin, Texas
$198k–$198k
6mo
Designing high-performance, energy-efficient interconnects for mobile, automotive, networking, and enterprise markets.
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Sr. Lead ASIC design Engineer - Digital Design
Nxp
Hyderabad
6mo
Define and implement hardware architectures optimized for AI inference SoCs, including custom-ISA processors and high-speed interconnects.
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Senior Out-of-Order CPU Architect
Intel
US, Texas, Austin
$191k–$191k
6mo
Define end-to-end CPU architecture specifications and microarchitectures for high-performance and low-power computing products.
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Senior ASIC Design Engineer
NVIDIA
US, CA, Santa Clara
$136k–$136k
6mo
Design and implement high-performance, area, and power-efficient RTL for world-leading SoCs and GPUs, including architecture and micro-architecture design.
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Hardware Engineering Manager
Hpe
Roseville, California, United States of America
$154k–$311k
6mo
Lead teams developing complex, high-performance networking hardware, ensuring technical excellence while driving predictable execution from concept through mass production.
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Automotive Senior Hardware Engineer / Specialist / Architect
Bosch-Group
coimbatore, in
6mo
Lead hardware design and development for vehicle computers, communication gateways, zone ECUs, and power distribution ECUs from concept to production.
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Lead Design Engineer
Cadence
BANGALORE
6mo
Lead Design Engineer responsible for RTL coding, datapath designs, complex FIFO design, and high-speed SerDes IP development.
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Lead Design Engineer - Physical Design
Cadence
BEIJING
6mo
Lead physical design implementation for high-speed digital DDR and HBM IP products targeting advanced process nodes (TSMC 3nm/5nm/7nm/12nm, Samsung 4nm/5nm/7nm/8nm/10nm) up to 6400MHz.
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Senior CPU Design Engineer
NVIDIA
US, OR, Hillsboro
$168k–$168k
6mo
Designing high-performance, low-power CPUs for product lines including consumer graphics, self-driving cars, and AI.
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Senior Digital/AMS Validation and Integration Engineer
Nxp
San Jose (Holger Way)
$166k–$166k
6mo
Design and integrate RTL for control loops, calibration engines, and high-speed data paths in 10G+ Automotive SerDes transceivers, bridging digital logic with analog front-ends.
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FPGA Design Engineer
Hpe
Singapore, Central Singapore, Singapore
6mo
End-to-end FPGA/PLD development for high-speed digital circuit designs in state-of-the-art networking products.
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Design Manager
ON Semiconductor
Bangalore, Karnataka, India
6mo
Lead and manage a new product design team to develop digital compute products, including MCUs, DSPs, and hardware accelerators, while benchmarking systems for various applications.
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System Design Engineer
NVIDIA
Taiwan, Taipei
6mo
Design and execution of next-generation NVIDIA products including GeForce, Virtualization, Datacenter, and Automotive platforms centered on GPUs, DPUs, CPUs, and LPUs.
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Sr. Staff Memory Design Engineer
MediaTek
San Jose, CA
6mo
Designing custom high-performance memory circuits (TCAM, SRAM, CPU caches) and advancing DTCO optimization techniques for next-generation ASICs targeting Cloud AI and Data Center applications.
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Staff/Senior Staff Physical Design Floorplan & PDN Lead
Enchargeai36
India
6mo
Architecting chip-level floorplans and Power Delivery Networks (PDN) for complex, large-scale SoCs to balance performance, power, and area.
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Sr Engineer, Design Enablement
Renesas-Electronics
Hyderabad, in
6mo
Develop and define Synthesis & Static Timing Analysis (STA) flows and methodologies for Advanced SoCs and MCUs on low geometry nodes (3/5/16/22nm).
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<Data Center>High-Speed Digital IC Design & Integration Engineer
MediaTek
HsinChu
6mo
High-speed digital IC design implementation and integration from RTL to gate level.
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Principal Engineer, Architecture/Chip Leader
Renesas-Electronics
Kodaira, jp
6mo
Lead the SoC/MCU architecture team to define system architecture and technical specifications for high-performance System-on-Chip and Microcontroller Unit products.
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Principal Engineer of SoC/MCU Architecture
Renesas-Electronics
Kodaira, jp
6mo
Define SoC/MCU architectures and detailed technical specifications for high-performance chips used in autonomous driving systems, serving business, product marketing, and system architects.
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Senior FPGA Engineer (w/m/d)
Trumpf
Remote
6mo
Designing digital hardware solutions and FPGA architectures for device platforms, from concept to implementation, ensuring optimal integration with RF and power electronics.
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Staff/ Sr Staff Engineer, Physical Design
Renesas-Electronics
Noida, in
6mo
Own RTL synthesis from elaboration to final sign-off, perform logic equivalence checks (LEC), develop and debug UPF, and manage power domains for complex SoC designs.
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Static Timing Analysis Engineer
Accenture
Bengaluru
6mo
Analyze and verify the timing of digital circuits to ensure they meet performance requirements under various operating conditions.
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IP RTL Design Engineer
Samsung Electronics
SSIR, Goldstone, Bangalore, India
6mo
Senior IP Design Engineer developing RTL, synthesis, and verification for complex Image Sensor IP modules.
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