Senior STA Lead
Core
Lead static timing analysis (STA) strategy and execution for advanced 3GHz+ CPU projects, ensuring first-time-right silicon sign-off.
Role type
Senior STA Lead (IC)
Builds
High-frequency CPU silicon
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis (STA), PrimeTime, PrimeClosure, OCV/POCV, MMMC, hierarchical timing, DVFS, asynchronous domain analysis, TCL scripting, Python scripting, cross-functional collaboration, technical leadership
Preferred skills
EDA tool advancements, industry trends, flow automation, risk mitigation planning
Technologies
PrimeTime, PrimeClosure, TCL, Python
Responsibilities
Oversee full-chip and block-level STA sign-off; define and implement advanced timing analysis methodologies; guide resolution of complex timing closure challenges; collaborate with Architecture, RTL, DFT, Analog, and Physical Design teams; lead technical reviews and sign-off readiness assessments; drive automation of timing analysis and ECO generation.
Seniority
Senior, hands-on IC
