Physical Design Student
Core
Support the physical implementation journey for complex semiconductor chips solving data bottlenecks for AI at scale.
Role type
Student physical design engineer (backend execution)
Builds
Custom connectivity solutions and standards-based semiconductor chips
Domain
Semiconductor hardware / AI infrastructure
Deliverable
production ML models
Required skills
Synthesis, floorplanning, Place & Route (P&R), Clock-Tree Synthesis (CTS), Static Timing Analysis (STA), Physical Verification (DRC/LVS), Reliability analysis (EMIR), Logic Equivalence Checking (LEC), scripting (Python/TCL/Bash/Perl)
Preferred skills
VLSI/Hardware student experience, hands-on EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus), basic verification concepts
Technologies
Synopsys Fusion Compiler, ICC2, Cadence Innovus
Responsibilities
Partner with senior engineers to support synthesis, floorplanning, P&R, and CTS; Assist in macro-level implementation and complex layout routing; Run engineering checks for design integrity including STA, DRC/LVS, and EMIR; Leverage scripting tools to automate tasks; Collaborate with Architecture, Design, and DFT teams
Seniority
Student, hands-on IC
