Silicon Engineer II
Core
Own execution from synthesis to place and route, including timing signoff, physical verification, EMIR, formal equivalence, and low power verification for design partitions.
Role type
Senior IC silicon engineer (physical design)
Builds
Large SoC/CPU/IP designs
Domain
Semiconductor design / VLSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Synthesis, floor planning, place and route, timing signoff, physical verification, EMIR, formal equivalence, low power verification, timing closure, power/performance/area tradeoffs, CTS techniques, multi-voltage/multi-powerdomain design, EDA tools (Fusion Compiler, Primetime, StarRC, RedHawk, Formality), scripting (Tcl, Perl, Python)
Preferred skills
Python expertise, PD flow flush experience, PD-TFM methodology knowledge
Technologies
Fusion Compiler, Primetime, StarRC, RedHawk, Formality
Responsibilities
Optimize blocks for Power, Performance, and Area; execute PD flow from synthesis to signoff; collaborate with PD flow/CAD and RTL teams to resolve design issues; generate constraints and perform timing optimization; implement VA planning and power grid planning in low power designs.
Seniority
Senior, hands-on IC