Staff/ Principal Physical Design STA Engineer
Core
Execute Static Timing Analysis (STA) flow and sign-off methodologies for complex semiconductor chips enabling rack-scale AI infrastructure.
Role type
Staff/Principal Physical Design STA Engineer
Builds
Custom connectivity solutions (CXL, Ethernet, NVLink, PCIe, UALink) for hyperscalers and data centers
Domain
Semiconductor / AI Infrastructure / High-Performance Computing
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), SDC constraint development, advanced margining (OCV, AOCV, POCV), physical design flows (Synthesis, P&R, Verification), cross-chip clock distribution analysis
Preferred skills
Timing Constraints Manager (Synopsys), TimeVision (Ausdia), Macro-level design validation, scripting (Tcl, Python, Perl)
Technologies
Synopsys, Ausdia, Tcl, Python, Perl
Responsibilities
Execute STA flow and sign-off methodologies; Collaborate with Architecture, Design, DFT, and Backend teams; Develop and optimize complex SDC constraints; Analyze and resolve cross-chip clock distribution challenges; Participate in design methodology improvements and tool automation
Seniority
Staff/Principal, hands-on IC
