Staff/ Principal Physical Design Engineer - SoC EMIR Expert
Core
Backend power methodologies and SoC EMIR analysis to ensure power robustness and reliability for high-performance AI connectivity silicon.
Role type
Staff/Principal Physical Design Engineer (SoC EMIR Expert)
Builds
High-performance connectivity chips (CXL, Ethernet, NVLink, PCIe, UALink) for AI infrastructure
Domain
Semiconductor / AI Infrastructure / Power Integrity
Deliverable
production ML models
Required skills
EMIR/Power Integrity analysis, IR drop analysis, signal/power electromigration (EM), Ansys RedHawk/Cadence Voltus, advanced FinFET nodes (7nm/5nm/3nm), Place & Route flows, power grid synthesis, RC extraction, standard cell architecture, EMIR methodology definition, root-cause analysis for voltage drop/EM, thermal analysis, statistical EM, TCL scripting for STA/Fusion Compiler
Preferred skills
Chip-Package co-analysis (CPM), timing convergence, sign-off criteria for high-volume production, packaging/top metal layers/MIM capacitors, ESD/CDM closure, latch-up, timing and P&R, ESD (including full CDM closure)
Technologies
Ansys RedHawk, RedHawk-SC, Cadence Voltus, TSMC sub-N5 technologies, Fusion Compiler, STA
Responsibilities
Perform IR drop and signal/power electromigration analysis on complex chips; Collaborate with Physical Design team for power integrity; Own IR architecture for timing convergence; Partner with Package Design engineers for Chip-Package co-analysis; Identify root causes for voltage drop violations and EM risks; Serve as go-to person for IR related issues
Seniority
Staff/Principal, hands-on IC
