Tech Lead Physical Design Engineer, Power Integrity
Core
Own IR drop and electromigration (IR/EMIR) analysis and closure across connectivity ASIC portfolio from floorplan to tapeout to ensure stable power delivery.
Role type
Technical Lead Physical Design Engineer (Power Integrity)
Builds
Connectivity ASICs for rack-scale AI infrastructure
Domain
Semiconductor / Power Integrity / AI Infrastructure
Deliverable
production ML models
Required skills
IR drop analysis, electromigration analysis, power grid design, PDN analysis, foundry sign-off criteria, Tcl scripting, Python scripting, Perl scripting
Preferred skills
SerDes power integrity, Ethernet PHY power integrity, PCIe power integrity, package-level power delivery analysis, multi-die integration
Technologies
Cadence Voltus, Synopsys RedHawk-SC, Synopsys PrimeTime PX
Responsibilities
Own static and dynamic IR drop and electromigration analysis at block and full-chip levels, Drive UPF-based power domain planning and power-aware sign-off, Analyze thermal and current density issues and recommend design modifications, Collaborate with package, power grid, and floorplan teams to resolve voltage drop hotspots, Provide actionable feedback on power grid reinforcement and decap strategy, Develop and refine EMIR runsets, stimulus methodologies, and reporting dashboards
Seniority
Senior, hands-on IC