Principal Physical Design Engineer, Methodology
Core
Define, develop, and maintain reusable physical design flows and automation infrastructure for the entire Physical Design (PD) team to enable faster, better tapeouts of complex SoCs.
Role type
Principal Physical Design Engineer (Methodology)
Builds
Reusable RTL-to-GDSII flow infrastructure, automation scripts, and multi-corner/multi-mode analysis frameworks for advanced node SoCs.
Domain
Semiconductor Physical Design, EDA, Advanced Node SoC Development
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure
Required skills
Physical design methodology, CAD flow development, Synthesis, Place-and-Route, Extraction, Static Timing Analysis (STA), Equivalence Checking, Multi-vendor toolchain integration, Python/Tcl/Perl scripting, Multi-corner/multi-mode analysis, Foundry design rules and enablement kits
Preferred skills
Agentic AI for EDA automation, CI/CD integration for physical design, Compute farm management, Advanced packaging or multi-die integration
Technologies
Cadence Innovus, Tempus, Voltus, Pegasus, Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC
Responsibilities
Define and maintain end-to-end RTL-to-GDSII flows spanning synthesis, place-and-route, extraction, STA, and EMIR; Build and enhance automation scripts for large-scale multi-corner/multi-mode STA and EMIR runs; Establish best practices, runset standards, and quality checks for concurrent tapeout programs; Support PD engineers with flow issues and methodology guidance; Drive adoption of flow improvements through training and documentation.
Seniority
Principal, hands-on IC with team scaling focus
