Technical Lead Physical Design Engineer
Core
Drive end-to-end static timing analysis (STA) ownership and timing closure for complex SoCs in connectivity ASICs.
Role type
Senior IC physical design engineer (timing analysis)
Builds
Connectivity ASICs for hyperscalers, server, and network OEMs
Domain
Semiconductor hardware design, advanced process nodes (7nm and below)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis (STA), timing closure, SDC constraints, multi-corner/multi-mode analysis, Tcl/Python/Perl scripting, Cadence/Synopsys toolchains, SoC design flows
Preferred skills
High-speed SERDES timing, ECO methodologies, DFT tools, IP integration, SystemVerilog/Verilog
Technologies
Cadence, Synopsys, TSMC 7nm, CXL, Ethernet, NVLink, PCIe, UALink
Responsibilities
Drive timing closure from RTL through sign-off; Develop and validate SDC constraints including MMMC setup; Define and manage I/O timing budgets across hierarchical designs; Apply advanced sign-off methodologies including OCV/AOCV and PVT effects; Manage large-scale multi-corner/multi-mode STA runs with automation; Generate and validate timing ECOs; Partner with design, implementation, and verification teams for timing convergence
Seniority
Senior, hands-on IC
