Senior Physical Design Engineer
Core
Own complete physical design execution for medium to large-size SOC blocks, driving end-to-end flow from synthesis through place-and-route and all signoff stages.
Role type
Senior Physical Design Engineer (SOC)
Builds
SOC blocks and subsystems for semiconductor chips
Domain
Semiconductor / Physical Design / Low Power Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SOC low power design methodology, PPA optimization, RTL to GDS implementation, synthesis, floorplanning, place and route, timing signoff, physical verification, EMIR signoff, formal equivalence, low-power verification, advanced foundry process nodes, PrimePower, data-driven flow optimization
Preferred skills
Cross-functional collaboration, problem-solving, data analysis
Technologies
PrimePower, EDA tools
Responsibilities
Drive methodology exploration to optimize SOC blocks for PPA; Coordinate with CAD, RTL, DFT, Architecture, and Technology teams; Ensure completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification; Influence design tools, flows, and methodologies; Own complete PD execution of medium to large-size SOC blocks; Partner with PD flow/CAD and methodology teams to fix TFM issues.
Seniority
Senior, hands-on IC
