Staff Physical Design Engineer - SoC EMIR Engineer
Core
Backend power methodologies and EMIR analysis for high-performance SoCs in advanced FinFET nodes to ensure power robustness and reliability for AI clusters.
Role type
Staff Physical Design Engineer (SoC EMIR)
Builds
High-performance connectivity silicon for rack-scale AI infrastructure
Domain
Semiconductor / AI Infrastructure / Power Integrity
Deliverable
production ML models
Required skills
EMIR analysis, IR drop analysis, signal/power electromigration, Ansys RedHawk, Cadence Voltus, advanced FinFET node expertise, Place & Route flows, power grid synthesis, RC extraction, standard cell architecture, TCL scripting
Preferred skills
Thermal analysis, sign-off criteria, timing analysis, packaging knowledge, MIM capacitor usage, power distribution networks
