Senior Full Chip Layout and Physical Verification CAD Engineer
Core
Developing full-chip physical design methodologies and physical verification flows for high-speed networking chips and SOCs.
Role type
Senior IC physical design and verification engineer
Builds
Networking chips and System-on-Chips (SOCs)
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full-chip layout, Physical verification (DRC/LVS/ANT/ERC/DFM), Python, Tcl, Shell, Make scripting, Linux environments, EDA tools (Synopsys ICC2/FC, Cadence Innovus, Synopsys ICV, Siemens Calibre)
Preferred skills
Data collection and analysis, Methodology definition/flow ownership for Full-chip/Place and Route
Technologies
Synopsys ICC2/FC, Cadence Innovus, Synopsys ICV, Siemens Calibre
Responsibilities
Develop full-chip physical design methodologies, run and debug physical verification flows, collaborate with layout and block owners for convergence, create solutions for advanced physical design problems.
Seniority
Senior, hands-on IC
