DFT Engineer
Core
Design and implement Design-for-Testability (DFT) architectures and strategies for next-generation AI connectivity chips to ensure silicon reliability and testability.
Role type
Senior IC DFT Engineer (Semiconductor)
Builds
High-end semiconductor chips for AI infrastructure connectivity
Domain
Semiconductor / AI Infrastructure / Deep-submicron processes
Deliverable
production ML models
Required skills
DFT architecture definition, JTAG/iJTAG, MBIST, Scan, ATPG, Static Timing Analysis (STA), gate-level simulation, test pattern generation, automation scripting (Tcl, Perl, Python, Shell), RTL design, backend implementation
Preferred skills
EDA tools (Synopsys TestMAX, Siemens Tessent), chip bring-up, mass production activities, advanced process technologies (7nm and below), high-speed interface protocols (PCIe, Ethernet, CXL, UALink)
Responsibilities
Define DFT architecture from high-level strategy to backend implementation; develop and optimize test/debug patterns; perform STA for DFT modes; collaborate with Architecture, Verification, and Backend teams; automate DFT implementation flows
Seniority
Senior, hands-on IC
