Senior Silicon Design Engineer
Core
Design high-performance, high-bandwidth Network-on-Chip (NoC) architectures and RTL for start-of-the-art AI SoCs.
Role type
Senior Silicon Design Engineer (NoC/SoC)
Builds
AI SoCs with integrated NoC subsystems
Domain
Semiconductor / AI Hardware
Deliverable
production ML models | product features
Required skills
NoC microarchitecture specification, RTL design (Verilog/System Verilog), Synthesis, Timing closure (CDC/LINT), PPA trade-offs, SOC integration, AXI/APB/JTAG interfaces, System Verilog assertions, Perl/Python scripting
Preferred skills
Post-Silicon Debug, Deep sub-micron tapeout experience
Technologies
Verilog, System Verilog, SDC, UPF, Perl, Python
Responsibilities
Define IP microarchitecture specifications, perform RTL coding and synthesis, manage timing constraints and PPA optimization, integrate subsystems into SoC, write verification assertions and coverpoints, debug post-silicon issues
Seniority
Senior, hands-on IC
