IP RTL Senior Design Engineer
Core
Develop high-quality intellectual property (IP) logic designs, register transfer level (RTL) coding, and simulations for Unified Intel Chassis designs, focusing on protocol bridges, access control, and reliability features.
Role type
Senior IC IP RTL Design Engineer
Builds
IP blocks, functional units, and subsystems for SoC designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
Verilog, System Verilog, RTL design, digital design principles, timing analysis, power optimization, area trade-offs, EDA tools (Synopsys, Cadence, Mentor Graphics), IP block integration, AXI/AXI-Lite/APB protocols, parity/ECC schemes, RAS concepts, secure MMIO, access-control logic
Preferred skills
UVM, formal verification, architecture and microarchitecture definition, complex IP logic design for high-performance applications
Technologies
Verilog, System Verilog, Synopsys, Cadence, Mentor Graphics, AXI, APB, UVM
Responsibilities
Develop logic designs, RTL coding, and simulations for IP blocks; Define architecture and microarchitecture features; Optimize RTL for power, performance, area, and timing; Support SoC customers with IP integration and verification; Drive compliance with quality assurance standards for IP handoff
Seniority
Senior, hands-on IC
