Director, Physical Design
Core
Lead and build a high-performing Physical Design team in Hyderabad to drive silicon success for complex, high-speed connectivity ASICs from RTL to GDSII.
Role type
Senior leadership IC physical design director
Builds
Custom connectivity ASICs (SerDes, high-speed PHYs, die-to-die interfaces) for AI and cloud infrastructure
Domain
Semiconductor / ASIC Physical Design / High-speed Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full-chip physical design (floorplanning, PnR, CTS, STA, IR/EM analysis, physical verification), EDA tool expertise (Cadence Innovus, Synopsys Fusion Compiler/IC Compiler, PrimeTime, Calibre, RedHawk/Voltus, StarRC), scripting (Tcl, Python, Perl), tapeout management, cross-functional team leadership
Preferred skills
Chiplet architecture and UCIe interfaces, low-power design (UPF/CPF), TSMC advanced node tapeout experience, networking/storage/AI/ML SoC background, establishing a PD center of excellence
Technologies
Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, RedHawk, Voltus, StarRC, Tcl, Python, Perl
Responsibilities
Build and mentor a global Physical Design team across PnR, STA, EMIR/Power Integrity, and CAD functions; Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII signoff; Lead timing closure across multiple corners and modes at advanced nodes (5nm and below); Oversee power integrity and reliability analysis to meet design quality targets; Manage tapeout schedules and cross-functional dependencies; Establish and improve PD flows, methodologies, and best practices for first-pass success
Seniority
Director, hands-on IC leadership
