ASIC Physical Design
1,423 open positions
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Low Power Design Engineer↗ North American Production SharingTijuana, BCN, MX 1mo Design adaptive power management controllers, on-chip sensor controllers, and digital power meters for wireless and automotive SoC chips.
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Physical Design Engineer Intern MonolithicpowerBarcelona, Spain 1mo Assist in the development, design, and physical implementation of digital and mixed-signal ICs utilizing leading edge technologies.
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Physical Design Methodology Engineer, AI HW IP TenstorrentAustin $100k–$100k1mo Develops, deploys, and owns the RTL-to-GDSII methodology for AI hardware IP physical design teams to ensure new blocks start from a working flow.
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SoC Architect WaymoMountain View (US-MTV-EMF690) $251k–$251k1mo Architect and create high-performance custom silicon and system-level compute architectures for Waymo's fully autonomous vehicle software stack.
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Senior FPGA Engineer, Cyber AndurilindustriesWashington, DC (999) $166k–$166k1mo Design and implement high-throughput FPGA datapaths, packetization pipelines, timing-sensitive interfaces, and hardware-near acceleration blocks for offensive cyber missions.
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Principal AI Silicon Architect MicrosoftUnited States, California, Mountain View 1mo Define high-performance silicon architecture specifications for AI accelerators and guide end-to-end silicon development cycles.
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Physical Design Engineer AxiadoHyderabad, TS, in 1mo Backend implementation engineer responsible for floorplanning, placement, CTS, routing, timing closure, and physical signoff for ASIC chips.
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Principal Engineer PD AsteralabsSingapore City 1mo Senior Physical Design Engineer developing next-generation transceiver IPs for high-speed connectivity in advanced technology nodes.
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SeniorFPGA Developer↗ LuxoftRemote 1mo Define and drive end-to-end FPGA architecture for state-of-the-art Communications Test & Measurement products, serving telecommunications, cloud, enterprise, and defense sectors.
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Principal SoC Chip Lead NxpShanghai (Pudong), CN 1mo Own SoC program execution from project definition through tape-out and post-silicon support, ensuring on-time delivery and coordinating engineering support during silicon bring-up and validation.
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Engineer↗ QualcommMarkham, ON, CA $90k–$90k1mo Physical Design Engineer contributing to the implementation of cutting-edge DSP cores for next-generation mobile, compute, and AI-enabled products.
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MTS, AI Optimized Memory Digital Design Engineer MicronFolsom, CA, US $175k–$175k1mo Design and implement high-performance, silicon-proven memory architectures for AI workloads, translating architectural vision into efficient hardware.
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Senior Hardware Engineer NVIDIAIsrael, Raanana 1mo Lead system and board design for GPU networking infrastructure (NVLINK) enabling high-bandwidth connectivity for next-generation AI and data center servers.
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Senior Director Design Manager↗ Analog DevicesKA, IN 1mo Lead end-to-end execution of complex SoC and processor programs from concept to commercialization, combining chip lead, technical program leader, and business stakeholder manager responsibilities.
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Designer, Systems (Computer)↗ Starfive International Pte. Ltd.Clementi, S00, SG 1mo Design, implement, and improve RTL modules for next-generation high-performance RISC-V CPUs and SoC chips.
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2027校招 - 数字IC设计工程师 / Digital Design Engineer Texas InstrumentsShanghai, China 1mo Architect new TI products by defining, designing, modeling, and verifying digital circuits including 64-bit DSP processors, MMUs, and heterogeneous multicore shared memory/cache systems.
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Senior/ IC Design Engineer (Physical Design)↗ Aurexis Tech Pte. Ltd.Singapore, S00, SG 1mo Perform RTL-to-GDS physical implementation for ASIC IP/subsystem/SoC designs, executing synthesis, DFT, and timing closure strategies while leveraging AI-assisted methodologies.
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Senior RTL Design Engineer, TPU↗
GoogleSunnyvale, CA, US
$163k–$163k1mo
Design RTL Intellectual Property (IP) for management and control subsystems in SoC-level data center accelerators, focusing on clocking, reset, error handling, and chip management.
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Core Performance Architect SifiveSanta Clara, California, United States $179k–$179k1mo Research and develop next-generation high-performance processors and micro-architectures to meet aggressive performance targets.
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Senior Staff / Principal SOC Floorplan Lead Enchargeai36India 1mo Own the physical foundation of next-generation AI and Data Center SoCs, bridging architecture, logic design, and physical design to achieve best-in-class Power, Performance, and Area (PPA).
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Hardware Engineer (FPGA/ASIC) JanestreetLondon 1mo Intern role focused on using programming language technology (OCaml/Hardcaml) to improve the design, testing, and validation of hardware designs.
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Staff Engineer, Physical Design MarvellHsinchu City 1mo Physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS processes for server, 5G/6G, and networking applications.
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ASIC Chip Design Engineer (3D Visual Language Model Robotics Chip Development)↗ O-HiveUniversity of Windsor, ON, CA 1mo Design and implement digital ASIC blocks and hardware accelerators for a 3D Visual Language Model processor to enable real-time robotics perception and control.
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SMTS Logic Design↗ RambusMontréal, QC, CA 1mo Senior Logic Design Engineer developing next-generation PCIe Gen6/Gen7 switch IP, covering architecture definition, micro-architecture, RTL implementation, and design closure.
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AI-Driven ASIC Physical Design Principal Engineer CiscoSan Jose, California, US $251k–$251k1mo Principal AI engineer building agentic physical design workflows and LLM-based copilots to automate ASIC physical design tasks like placement, routing, and timing analysis.
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Senior FPGA Engineer — Wireless Networking Group (WNG)↗ Imdea Networks InstituteMadrid, MD, ES 1mo Lead FPGA design for next-gen Integrated Sensing and Communication (ISAC) prototyping platforms, integrating advanced algorithms and machine learning for real-time RF and channel data processing.
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Digital Design Engineer – AI Accelerators StmicroelectronicsGreater Noida, India 1mo Design and implement high-throughput compute datapaths and microarchitectures for AI accelerator chips, integrating compute blocks with memory interfaces.
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Chip Design Engineer, Nitro Chip Design Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
1mo
Design and develop custom silicon micro-architecture and RTL for the Nitro System on Chip (SoC) that underpins AWS cloud instances.
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Director - Digital Subsystem Solutions↗ Infineon Technologies 1mo Lead multiple teams to define architecture, drive RTL design, and oversee verification for digital IC/SoC blocks.
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Hardware Engineer Western-DigitalSan Jose, CA, us 1mo Design custom silicon, electronic hardware, embedded firmware, and mechanical systems for next-generation hard disk drives and data storage products.
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