Physical Design Engineering, VP
Core
Lead end-to-end physical design execution for complex multi-die switching products featuring UCIe and UALink connectivity to enable rack-scale AI infrastructure.
Role type
VP of Physical Design (Strategic Leadership & Hands-on IC)
Builds
Next-generation switching products with UCIe and UALink technologies for hyperscale AI data centers
Domain
Semiconductor / AI Infrastructure / High-Speed Connectivity
Deliverable
production ML models | product features
Required skills
Physical design leadership, chip-level floorplanning, power planning, placement, routing, timing closure, interposer design, die-to-die interfaces, advanced packaging (2.5D/3D integration), physical design flows, signoff methodologies, team scaling
Preferred skills
UCIe, PCIe Gen 6/7, high-speed SerDes, AI/ML infrastructure, networking ASICs, Cadence/Synopsys tools, DFT integration, design for manufacturability (DFM), automation innovation
Technologies
UCIe, UALink, PCIe Gen 6/7, Cadence, Synopsys
Responsibilities
Lead end-to-end physical design execution for complex multi-die switching products; Drive chip-level floorplanning, power planning, placement, routing, and timing closure; Establish physical design methodologies for interposer-based chiplet architectures; Scale and develop a world-class physical design organization; Partner with architecture, digital design, packaging, and silicon engineering teams; Drive resolution of critical timing, power, and signal integrity challenges
Seniority
VP, Strategic Leadership & Hands-on IC
