HBM Logic Architect
Core
Establishing US-based HBM Architect Design team to address base-die architectural challenges in HBM and 3D-stacked DRAM for key customers.
Role type
Senior IC HBM Logic Architect
Builds
HBM and 3D-stacked DRAM architectures and digital IP
Domain
Semiconductor, Memory, High-speed digital PHY
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design and implementation, Digital IP definition and validation, Cross-functional collaboration, Architecture decision-making, PPA optimization, System-level co-optimization
Preferred skills
High-speed digital PHY design, DRAM memory controller design, DRAM DFT/DFD architecture, PHY/TSV bit macro design, 3D PHY design
Technologies
ASIC/SoC, RTL, Digital IP, HBM, 3D-stacked DRAM, TSV
Responsibilities
Define, design, and validate digital IP for ASIC/SoC products; Perform RTL design and implementation based on approved specifications; Collaborate with cross-functional teams to define IP functionality, behavior, and architecture; Review digital IP requirements and evaluate architecture options based on PPA targets; Determine or contribute to architecture decisions for digital IP implementation; Develop and verify RTL designs using industry-standard design methodologies; Provide design guidance and support for physical design implementation; Drive system-level co-optimization beyond standalone DRAM design; Build deep technical partnerships with U.S.-based customers.
Seniority
Senior, hands-on IC