Senior ASIC Design Engineer
Core
Designing digital blocks for high-performance AI infrastructure connectivity chips, owning the journey from high-level definition through RTL implementation and backend support.
Role type
Senior IC ASIC Design Engineer (Digital)
Builds
Custom connectivity solutions and standards-based chips for AI infrastructure
Domain
Semiconductor / AI Infrastructure / High-speed connectivity
Deliverable
production ML models | product features
Required skills
Verilog, SystemVerilog, RTL coding, digital design principles, micro-architecture, EDA tools (Lint, CDC, Synthesis, Timing, Power), PPA optimization
Preferred skills
DDR and PCIe protocols, power management techniques, Clock Domain Crossing, simulation, debugging, Python, Perl, high-speed serial interface designs
Technologies
Verilog, SystemVerilog, Python, Perl, EDA tools
Responsibilities
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support; Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions; Serve as the point of contact for logic blocks, interacting with Architecture, Verification, and Backend teams; Utilize industry-leading EDA tools to ensure designs are robust, scalable, and power-efficient; Apply design techniques to meet PPA (Power, Performance, Area) targets; Participate in design methodology improvements and tool automation initiatives
Seniority
Senior, hands-on IC
