Senior Principal Digital Design Engineer
Core
Define micro-architecture strategies and lead RTL implementation for next-generation digital designs powering AI infrastructure connectivity.
Role type
Senior Principal Digital Design Engineer (IC)
Builds
High-performance silicon for AI connectivity solutions (PCIe, CXL, Ethernet, DDR)
Domain
Semiconductor / AI Infrastructure / High-Speed Protocols
Deliverable
production ML models | product features
Required skills
Micro-architecture definition, RTL coding, synthesis, timing closure, DFT methodologies, high-speed protocol expertise, advanced CMOS node design, CAD flow proficiency
Preferred skills
Multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink), embedded firmware collaboration, RISC-V or Arm subsystems, design methodology contributions, cross-functional leadership in data centers
Technologies
Cadence, Synopsys, PCIe, CXL, Ethernet, DDR4/DDR5, UALink, UCI, NVLink, CXL, PCIe Gen 6/7
Responsibilities
Define micro-architecture for complex digital blocks, lead RTL implementation from concept to silicon bring-up, drive timing constraints and closure strategies, partner with verification teams for test plans and coverage closure, mentor engineering teams, drive continuous improvement of silicon development processes
Seniority
Senior, hands-on IC with technical leadership
