ASIC Physical Design
1,420 open positions
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Principal Physical Design/Implementation Engineer↗ Marvell TechnologySanta Clara, CA, US $155k–$232k1mo Architect and lead next-generation physical design methodologies and automation flows for complex SubSystems within SoCs, delivering reference floor plans and timing-closed partitions.
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Senior Physical Design Interposer Engineer NVIDIAUS, CA, Santa Clara $136k–$136k1mo Build automated flows, methodologies, and tools to construct, analyze, and validate complex interposer designs for NVIDIA's multi-die platforms.
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SoC Design and Integration Engineer↗ QualcommTijuana, Baja California, Mexico 1mo Design and integration of high-performance System-on-Chip (SoC) architectures for mobile, AI, Compute, and XR applications using sub-5nm process nodes.
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RTL integration Engineer BroadcomUSA-CA San Jose Innovation Drive $144k–$144k1mo Perform IP integration, test/debug mode verification, and RTL design creation at the SoC level.
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Enterprise Hardware Engineering Technical Lead CiscoRTP, North Carolina, US $139k–$139k1mo Hardware board and system design engineer responsible for the full lifecycle of Cisco's Edge and Access routing products, from architecture and design through bring-up, validation, and production readiness.
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Staff FPGA Systems Development Engineer↗ Analog DevicesDurham, NC, US $125k–$125k1mo Develop and deploy high-quality FPGA and SoC solutions for electronic test equipment, wideband communication systems, and Aerospace & Defense subsystems.
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SystemC Modeling Developer (Remote)↗ UstRemote 1mo Design and develop SystemC/TLM models for next-generation Compute and AI server platforms to enable architecture exploration, performance analysis, and pre-silicon software development.
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Senior Design Engineer MicrosoftUnited States, California, Mountain View 1mo Designing high-performance, high-bandwidth Network-on-Chip (NoC) and AI SoC microarchitectures, including RTL design, synthesis, and SOC integration.
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Principal DFT Engineer (Silicon Engineering) SpaceXAustin - 800 1mo Lead implementation and optimization of DFT architectures for next-generation ASICs deployed in space and ground infrastructures to enable global connectivity.
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Tech Lead ASIC Design Engineer AsteralabsBengaluru 1mo Lead the architecture, RTL design, and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure connectivity products.
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Hardware Engineer JanestreetNew York 1mo Design and implement FPGA or ASIC applications using high-level hardware description languages and tools.
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Senior System Architecture Specialist↗ SynopsysPorto, P13, PT 1mo Customer-facing presales technical specialist defining UCIe/die-to-die subsystem architectures for complex ASIC, SoC, and multi-die platforms.
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Staff Digital Design Engineer NxpBangalore 1mo Lead architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies), driving digital micro-architecture, state machines, PCS…
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Systems Design Engineer, Digital Signal Processing↗
GoogleSunnyvale, CA, US
$192k–$192k1mo
Design and implement high-speed digital blocks for next-generation TPU (Tensor Processing Unit) hardware, transforming architectural specifications into bit-exact silicon for AI/ML acceleration.
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2027 Internship - FPGA Engineer Virtu FinancialDublin, Ireland 1mo Intern role focused on FPGA and ASIC design for ultra-low latency trading systems, working from architecture through RTL implementation, simulation, verification, and hardware bring-up.
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Senior Principal Engineer – Hardware Chip Lead, Connectivity BU MarvellSanta Clara, CA $182k–$273k1mo Lead end-to-end hardware design and program delivery for advanced optical DSP ASICs serving hyperscale data center, enterprise, and AI infrastructure markets.
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SDE - CPLD / FPGA
AmazonSeattle, Washington, United States
$144k–$194k1mo
Design, implement, verify, validate, deploy, and support programmable logic components (CPLD/FPGA) for AWS server infrastructure to ensure operational excellence and fleet health.
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Physical Design Methodology & Flow SambanovasystemsSan Jose, CA $180k–$180k1mo Lead the development and maintenance of physical design composition flows for state-of-the-art RDU chips optimized for machine learning and artificial intelligence.
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ASIC Digital Design Engineer Lead↗ AppleAustin, TX, US $167k–$167k2mo Lead technical engagements between Apple and silicon suppliers to define, develop, and productize next-generation display technologies for mobile devices.
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Principal Technical Program Manager – DSP/Mixed-Signal ASIC Development – TeraWave BlueoriginSan Diego, CA $249k–$249k2mo Lead end-to-end development of advanced mixed-signal/DSP ASICs and SoCs (including Digital Beamforming) for TeraWave's satellite communication system, spanning architecture definition through production.
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IP RTL Senior Design Engineer IntelIndia, Bangalore 2mo Develop high-quality intellectual property (IP) logic designs, register transfer level (RTL) coding, and simulations for Unified Intel Chassis designs, focusing on protocol bridges, access control, and reliability features.
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Microprocessor VLSI Physical Design Engineer↗ AMDFort Collins, CO, US 2mo Design high-speed VLSI circuits and optimize power, performance, area, and schedule for next-generation CPU cores and caches.
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Senior ASIC Design Engineer HpVancouver, Washington, United States of America $116k–$116k2mo Lead functional blocks and subsystems of digital ASICs from design to silicon verification for HP's main controller and proprietary IP in printers.
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Senior Principal Engineer, Hardware Application Engineering - Board & System Design↗ I8is Inc.Santa Clara, CA, US $200k–$200k2mo Senior technical authority guiding complex board and system hardware designs for advanced networking and AI infrastructure platforms, ensuring optimization for performance, reliability, and high-volume production.
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