ASIC Design Engineer Technical Lead
Core
Lead ASIC design for Cisco's core Switching, Routing, and Wireless products, defining architecture and implementing RTL to power AI-era hardware platforms.
Role type
Senior IC ASIC Design Technical Lead
Builds
Silicon One and other hardware platforms for global networking infrastructure
Domain
Networking hardware / ASIC design
Deliverable
production ML models | product features
Required skills
Verilog/System Verilog, micro-architecture development, timing closure, RTL implementation, simulation debugging, post-silicon validation
Preferred skills
Setup/hold timing violation resolution, scripting (Python/Perl/TCL), troubleshooting
Technologies
Verilog, System Verilog, Python, Perl, TCL
Responsibilities
Define chip architecture and micro-architecture specifications; Implement Verilog RTL meeting timing/performance; Mentor junior engineers; Collaborate with verification and physical design teams; Debug simulation and customer failures; Perform post-silicon validation tests
Seniority
Senior, hands-on IC with mentorship responsibilities
