Principal Digital Design Engineer
Core
Architect and implement next-generation digital designs for high-performance AI connectivity solutions, owning complex blocks from micro-architecture through silicon bring-up.
Role type
Principal Digital Design Engineer (Silicon/SoC)
Builds
Production-quality silicon for PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols
Domain
Semiconductor hardware design, AI infrastructure, high-speed interconnects
Deliverable
production ML models | product features
Required skills
Micro-architecture definition, RTL coding, timing closure, DFT implementation, high-speed protocol expertise (PCIe/CXL/Ethernet/DDR), advanced CMOS node design (≤7nm), CAD flow proficiency
Preferred skills
Embedded firmware collaboration, embedded processor subsystem knowledge (RISC-V/Arm), design methodology improvement, CAD automation
Technologies
Cadence, Synopsys, PCIe, CXL, UALink, UCI, Ethernet, DDR4, DDR5, 7nm CMOS
Responsibilities
Define micro-architecture and drive RTL implementation for complex digital blocks; Lead timing closure and DFT feature implementation; Collaborate with verification teams for test plans and coverage closure; Own third-party IP integration and block-level verification; Mentor junior engineers and contribute to silicon development processes
Seniority
Principal, hands-on IC with technical leadership
