Sr. Principal Digital Designer
Core
Lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products, including PCS pipelines, encoding/decoding logic, and safety mechanisms.
Role type
Sr. Principal Digital Designer (ASIC/SoC)
Builds
Automotive Ethernet PHY chips (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, multi‑gig SerDes)
Domain
Automotive semiconductors, high-speed digital communication
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production hardware/ASICs)
Required skills
Verilog/SystemVerilog RTL design, high-speed digital logic, state machines, IEEE 802.3 Ethernet PCS, synthesis, STA, CDC/RDC methodology, SoC design, safety mechanisms (BIST, watchdogs)
Preferred skills
Automotive Ethernet standards (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1), PHY firmware-driven initialization, post-silicon validation, safety-critical digital logic
Technologies
Verilog, SystemVerilog, IEEE 802.3, ISO 26262, AEC‑Q100
Responsibilities
Define digital subsystem micro-architecture for Automotive Ethernet PHYs; Develop high-quality RTL for control, datapath, and protocol logic; Translate system requirements and IEEE 802.3 specs into robust digital designs; Ensure compliance with Automotive Ethernet standards and ISO 26262; Mentor junior engineers and guide technical decision-making
Seniority
Sr. Principal, hands-on IC design & architecture
