Principal Physical Design Engineer, STA
Core
Drive end-to-end static timing analysis (STA) ownership for complex SoCs to ensure robust full-chip timing convergence for connectivity ASICs.
Role type
Principal Physical Design Engineer (STA)
Builds
Connectivity ASICs for hyperscalers, server, and network OEMs
Domain
Semiconductor physical design, advanced nodes (7nm and below)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis (STA), SDC constraints, multi-corner/multi-mode analysis, OCV/AOCV, PVT effects, hierarchical timing analysis, timing ECO generation, Tcl/Python/Perl scripting, synthesis, place-and-route, extraction, equivalence checking, Cadence/Synopsys toolchains
Preferred skills
High-speed SerDes timing, Ethernet PHY timing, ECO methodologies, DFT tools, IP vendor integration, SystemVerilog/Verilog
Technologies
Cadence, Synopsys, TSMC 7nm, ETM libraries
Responsibilities
Drive timing closure from RTL through sign-off, develop and validate SDC constraints, define I/O timing budgets, apply advanced sign-off methodologies, manage large-scale STA runs with automation, generate and validate timing ECOs, partner with design and verification teams for convergence
Seniority
Principal, hands-on IC
