ASIC Verification Engineering
935 open positions
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Verification Engineer↗ Hccm ConsultingLisboa, P11, PT 16d Develop and maintain constrained-random UVM testbenches for RTL blocks and full-chip verification, ensuring protocol compliance and coverage closure.
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Design Verification Engineer IntelUS, California, Santa Clara $106k–$106k16d Entry-level Design Verification Engineer building testbenches and constrained-random tests for next-generation interconnect and chassis IPs.
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Manager/Senior Manager - Design Verification MicronHyderabad - Phoenix Aquila, India 16d Lead design verification for complex full-chip gate-level custom designs in advanced low-power and power management technologies (DDR4, LPDDR4, DDR5, LPDDR5) operating at high speeds up to 9600MT/s.
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Principal Emulation Engineer AsteralabsSan Jose $207k–$230k16d Build and operate emulation environments to stress-test complex ASICs and SoCs before silicon, validating hardware-software interactions and high-speed protocols.
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Sr. Staff Engineer, SoC Design Verification TenstorrentBoston $100k–$100k16d Lead end-to-end design verification for advanced RISC-V CPU cores, caches, interconnects, and AI compute platforms.
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Design Verification Engineer（SoC機能検証エンジニア）(2) Renesas-ElectronicsKodaira, jp 17d Design Verification Engineer responsible for functional verification of SoC products for industrial equipment and physical AI, ensuring quality and reliability from IP to SoC level.
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Principal Engineer SoC Design Verification GlobalFoundriesIND - Karnataka - Bengaluru - North, IN 17d Define and drive verification strategy, methodology, planning, execution, and signoff for complex Smart Analog & Sensor SoCs to ensure first-pass silicon success.
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Principal EDA R&D Engineer NVIDIA5 Locations $232k–$232k17d Lead research, architecture, and development of core formal verification engines enhanced by Agentic AI frameworks to automate hardware verification at scale.
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System Modeling and Performance Validation Engineer↗ AMDSanta Clara, CA, US 17d Develop and integrate high-fidelity system models (transaction-level to cycle-accurate) for complex ASIC and SoC platforms to support architecture exploration, design validation, and software development acceleration.
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Senior Design/Verification Engineer SemtechCAN - Burlington, ON, CA $115k–$115k17d Senior IC verification engineer developing advanced digital subsystems within mixed-signal ICs for data communications and video broadcast.
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Senior Digital / Mixed-Signal IC Design or Verification Engineer BroadcomUSA-Mendota Heights-Northland $110k–$110k18d Develop advanced semiconductor devices (digital IC design or mixed-signal verification) for low-power, high-performance analog and mixed-signal products supporting high-capacity data center enterprise storage.
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Lead Product Engineer CadenceNOIDA 18d Lead Product Engineer for Hardware Emulation, analyzing customer requirements to improve compile and runtime performance in complex SoC verification environments.
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Associate Design Verification Engineer AnalogdevicesPhilippines, Cavite (jp) 18d Develop test benches and perform design verification for new digital, analog, and mixed-signal products prior to tape-out.
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FPGA Engineer/ FPGA Hardware Engineer (level 2 or 3) Employment InternationalMelbourne, Victoria 19d Develop RTL design code, verification strategies, and hardware test cases for ASIC/FPGA/SoPC developments, ensuring DO-254 DAL-A certification for Airborne Electronic Hardware.
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Digital Verification Engineer - MCU NxpCatania $38k–$38k19d Develop and execute comprehensive verification plans and environments to validate complex digital circuits for high-performance microcontrollers (MCUs) in industrial and IoT applications.
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Staff ASIC Verification Engineer ON SemiconductorBangalore, Karnataka, India 19d Ensure functional correctness, robustness, and quality of cutting-edge semiconductor and SoC designs through comprehensive verification planning, testbench development, and coverage closure.
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CPU Emulation Engineer QualcommUSA $167k–$167k20d Design and build test bench infrastructure in C/C++ and SystemVerilog to support CPU emulation across multiple platforms and verify high-performance CPUs.
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Analog Design Intern, MS - Summer 2027 MarvellSanta Clara, CA, US $79k–$158k22d Design and verify test chip experiments using Verilog simulation and develop automation scripts for hardware characterization and data analysis.
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Junior Verification Engineer AlteraJerusalem, Israel 22d Develop and verify high-speed SerDes IP (10Gbps to 100Gbps+) for PCIe, Ethernet, and other interfaces, focusing on digital/analog design, DSP pipelines, and firmware-hardware co-verification.
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New College Grad - HBM Digital Verification Engineer↗ Micron TechnologyTlaquepaque, JAL, MX 22d Verify advanced pre-silicon memory solutions, specifically High Bandwidth Memory (HBM) and emerging memory technologies, by simulating, analyzing, and debugging full-chip designs.
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Senior ASIC Engineer CiscoSan Jose, California, US $168k–$168k22d Defines, architects, designs, and verifies high-performance ASICs for Cisco's core Switching, Routing, and Wireless products.
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Principal/Team Lead, Digital Verification Engineer (FEC) CienaOttawa $133k–$133k22d Develop verification strategies, test plans, and testbenches to simulate and validate Forward Error Correction (FEC) functional blocks and subsystems for high-speed connectivity modems.
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Design Verification Engineer MicrosoftUnited States, North Carolina, Raleigh 22d Lead verification of components used in Fabric Interconnect, defining strategies and test plans to ensure design quality.
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Career Accelerator Program - Design Verification Engineer- Bachelors Texas InstrumentsDallas, TX, United States 23d Develop detailed verification plans, test benches, and simulations at RTL and GLS to ensure first-pass silicon success for TI's design and system teams.
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Senior Design Verification Engineer SifiveHyderabad, India 23d Own block- and subsystem-level design verification for advanced out-of-order (OoO) CPU cores, focusing on execution pipelines, memory systems, and coherence protocols.
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