ASIC Verification Engineering
1,774 open positions
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ASIC Digital Verification Engineer↗ Synopsys IncDublin, County Dublin, Ireland 9d Design, deploy, and maintain reusable UVM verification components and AI-assisted flows for PCIe and CXL controller IP used in data centers and AI applications.
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<GPU>GPU Design Verification Engineer MediaTekHsinChu 9d Develop verification environments, test plans, and test patterns for GPU, DSP, and peripheral IP designs to ensure functional correctness, low power, and performance.
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Product Engineer Siemens-EdaRemote $24k9d Drive scalability, deployability, and quality of the Questa® Advanced Simulator (a core simulation and debug engine for FPGA and SoC designs) while acting as the voice of the customer and supporting product adoption.
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Senior/Staff Design Verification Engineer↗ Bitdeer Technologies GroupSingapore, SG 9d Design Verification Engineer ensuring functional correctness and performance of computer arithmetic IPs (ASICs) for Bitcoin mining and AI cloud.
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Emulation Performance Methodology & Debug Engineer↗ QualcommTijuana, Baja California, Mexico 10d Develop and support pre-silicon SoC platforms using FPGA emulation to enable new chip designs before silicon fabrication.
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Design Verification Engineer MicrosoftUnited States, North Carolina, Raleigh 10d Develop UVM/System Verilog verification environments for fabric interconnect or memory subsystems, applying formal methods and generative AI to drive quality and efficiency.
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Formal Verification Lead Advanced Micro Devices, IncBangalore, India 10d Provide technical leadership for formal verification of complex, high-performance CPU cores, defining strategies, driving convergence/sign-off, and advancing methodologies for next-gen processor designs.
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Sr Engineer, Design Verification Renesas-ElectronicsBengaluru, KA, in 11d Develop verification testbench components for chip/module level using System Verilog and UVM to achieve 100% verification completeness before tape-out.
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Sr. Staff Engineer - Design Formal Verification SiFiveHyderabad, India 11d Own and drive strategies to verify complex processor modules (instruction fetch, branch prediction, execution pipelines) using formal verification techniques.
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Verification Engineer ArmChandler, Arizona $130k–$176k11d Develop SystemVerilog UVM and formal verification environments for block-level functional verification of CPU memory-system components.
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Staff Engineer Design InfineonBangalore BTP 11d Validate next-generation WLAN MAC designs for cutting-edge wireless products using industry-leading verification methodologies.
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Formal Verification Intern AppleMunich, Germany 11d Formal verification of System-on-a-chip (SoC) design blocks and IPs to ensure bug-free functionality for Apple products.
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Verification Lead for 4-Core Coherent System↗ SemidynamicsBarcelona, CT, ES 11d Lead verification strategy and execution for a 4-core coherent AI system with RISC-V CPUs, Vector/Tensor Units, and a memory engine, ensuring tape-out readiness.
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GPU Verification Engineer - AI SoC Development IntelIndia, Bangalore 11d Develop and execute scalable pre-silicon functional verification environments for AI System-on-Chip (SoC) designs to ensure functionality, reliability, and security before manufacturing.
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Senior Design Verification Engineer, Google Cloud↗
GoogleKA, IN
11d
Verify complex digital designs for AI/ML hardware acceleration, specifically TPU architecture and integration within AI/ML-driven systems.
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New College Grad - HBM Verification↗ Micron TechnologyTlaquepaque, Jalisco, Mexico 11d Provide verification support for pre-silicon full chip designs and develop test benches for HBM and emerging memory architectures.
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ASIC Design Verification Engineer - Slingshot HpeFt. Collins, Colorado, United States of America $115k–$218k12d Design Verification Engineer for HPE Slingshot interconnect ASICs used in HPC and AI systems, responsible for pre-silicon verification from test plan to sign-off.
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Lead Engineer – CAD Digital Verification SilabsHyderabad, IN 12d Develop, enhance, and support CAD tools and EDA simulation flows for efficient verification of semiconductor products (ASIC/SoC).
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Security HW Design Verification Engineer - (Visas Supported)↗ European Tech RecruitCork, County Cork, Ireland 12d Design and verify advanced Security IP for SoCs, delivering hardware root of trust and secure processing for mobile, compute, and data center products.
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Design Verification Engineer, Leo Payload FPGA
AmazonSunnyvale, California, United States
$177k–$247k12d
Create and maintain UVM-based verification environments and test suites for FPGA-based subsystems to verify digital designs for networking functions in a satellite communication system.
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Principal ASIC DFT Design Engineer - Terawave BlueoriginCentral Texas, US $269k–$377k12d Define DFT architecture and test strategy for large multi-block System on Chip (SOC) designs to ensure test quality and manufactability for the TeraWave satellite communications network.
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ASIC Verification Engineer BroadcomIND-Pune EON Kharadi Infrastructure, IN 12d Develop test plans, functional coverage, and scalable verification environments for Block/Core/SOC features using System Verilog and UVM.
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Staff Engineer - SerDes Verification↗ AMDTampines, S00, SG 12d Building UVM/SystemVerilog testbenches, running simulations, debugging timing/protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams for high-speed SerDes interfaces.
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Lead Emulation Test Engineer↗ Positron AIRemote $180k–$300k12d Lead pre-silicon validation and emulation strategy for next-generation AI inference ASICs using Cadence Palladium.
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Staff / Principal - Memory Circuit Design Verification MicronHyderabad, Telangana, India 12d Lead verification and end-to-end analysis of complex full-chip gate-level custom memory designs (DDR4/5, LPDDR4/5, HBM) operating at high speeds up to 6400MT/s.
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Senior Design Verification Engineer, AI Hardware TenstorrentBelgrade 13d Ensuring quality and reliability of digital designs for custom AI platforms through comprehensive verification methodologies.
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Ingénieur(e) Vérification Fonctionnelle FPGA/ASIC - Spatial - Toulouse Forums Talents HandicapHaute-Garonne, Occitanie 13d Functional verification engineer for embedded digital systems (FPGA/ASIC/SoC) in the space sector, ensuring compliance of deliverables for satellite constellations.
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