ASIC Verification Engineering
1,774 open positions
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Senior Digital ASIC Verification Engineer CienaOttawa, CA CA$112k–CA$179k6d Senior Digital ASIC Verification Engineer responsible for verifying complex, highly integrated digital ASICs, focusing on top-level functionality, cross-IP interactions, and system-level use cases.
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Staff Engineer (Multiple Openings) Samsung Electronics3655 N 1st St, San Jose, CA, USA $216k–$252k6d Lead verification of pixel pipe subsystems (scalar/vector ALUs, register files, instruction issue logic) for high-performance computing devices including mobile and automotive segments.
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DFT Engineering Director, CPU Cores Design for Testability Advanced Micro Devices, IncAustin, Texas 6d Senior technical leader driving Design for Testability (DFT) execution and roadmap for future AMD CPU cores from concept to production.
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Graduate ML Hardware Verification Engineer ARM Sweden ABLund, Sweden SEK 545k6d Graduate role focused on writing code and developing simulation testbenches to verify neural accelerators for machine learning applications before they reach silicon.
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Digital Verification Engineer (all genders) Ims-Nanofabrication-GMBHWien, Wien, at €70k7d Own verification strategy, testbench development, and sign-off readiness for assigned IPs, subsystems, or distributed systems.
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Internship - Chip Verification InfineonSingapore 7d Build chip verification methodology, infrastructure, and tooling for AI-enabled chip development.
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Design Verification Engineer Intern↗ Micron TechnologyTlaquepaque, JAL, MX 7d Support verification activities and develop digital/analog verification environments for advanced DRAM and emerging memory technologies.
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Digital Verification Engineer (all genders)↗ Ims NanofabricationWien, W, AT €70k7d Own verification strategy, testbench development, and sign-off readiness for assigned IPs, subsystems, or distributed systems in semiconductor mask writers.
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Verification Engineer - Networking IPs NVIDIAIndia, Bengaluru 7d Develop verification components and APIs for unit and cluster level testbenches to verify queuing and scheduling algorithms and designs for datacenter chips.
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Peripherals Design Verification - Staff Engineer QualcommBangalore, India 7d Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products.
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Sr. ASIC Design Verification Engineer CiscoSan Jose, California, US $168k7d Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure for Cisco high-end switching products.
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CPU Verification Engineer↗ AMDDublin, County Dublin, Ireland 7d Lead and execute functional verification of high-speed Microprocessor designs, including development of infrastructure and test suites at behavioral RTL and gate design levels.
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Wireless Design Verification Engineer AppleSan Diego, United States of America 7d Verify Radio digital controllers and RF subsystems for WiFi SoCs to ensure first-time-right silicon success.
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Senior ASIC Verification Engineer HpeHeredia, Heredia, Costa Rica 7d Verifies, analyzes, develops, modifies, and evaluates VLSI components and hardware systems; determines design verification through software simulation and builds physical implementations through multidimensional design layouts.
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Principal Product Engineer(DVT) Siemens-EdaSeongnam, KOR, South Korea 7d Define product features and methodologies for Siemens Functional Verification tools to address verification challenges in chip, board, and system design.
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Digital Verification Intern - Spring 2027 NxpChandler (Office), US 7d Intern supporting IP design and verification teams to ensure SoC and IP delivery on time and with high quality.
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Lead Digital Verification Engineer CadenceMOUNT-ROYAL (Montreal), CA CA$90k–CA$166k7d Lead verification engineer developing high-performance physical IP for industry-standard protocols, responsible for verifying digital RTL and building reusable verification components.
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Staff Engineer, DFT AmbiqmicroincAustin HQ 7d Designing and implementing low-power Design for Test (DFT) architectures and infrastructure for ultra-low power System-on-Chip (SoC) devices based on subthreshold operation.
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Design Verification Engineer II MicrosoftIndia, Karnataka, Bangalore 8d Design Verification Engineer responsible for creating constrained-random verification environments, formal verification, and debugging complex CPU or SoC IP designs to ensure functional correctness before tape-out.
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R&D Engineer IC Design BroadcomIND-Bangalore Electronic City - S1, IN 8d Design and verification of DFT (Design for Test) architectures, test insertion, pattern generation, and post-silicon debug for Broadcom ASIC SoC designs.
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Design Verification Engineer (2027 New College Graduate) GlobalFoundriesUSA - Texas - Richardson $86k–$148k8d Functional verification of CPU cores and related subsystems, focusing on core functionality, performance, and modeling.
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ASIC Verification Engineer↗ BullMadrid, Community of Madrid, Spain 8d Verify complex ASICs (network controllers, routers, cache coherence controllers) for high-performance Bull servers using constraint-random, coverage-driven methodologies.
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SoC Verification Engineer ArmSheffield, United Kingdom 8d Develop and execute test plans and verification methodologies for complex SoC-level designs, ensuring seamless interaction between hardware and software layers.
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CPU Design Verification Engineer II SiFiveHyderabad, India 8d Verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout, focusing on block and core-level validation including pipeline hazards, memory-ordering violations, and speculation corner cases.
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Eng II - Elec BAE SystemsLondon, England, GB 9d FPGA Verification engineer developing high-reliability electronic systems and space payloads using FPGA SoC architectures, digital filters, and image processing.
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ASIC Digital Verification, Sr. Manager↗ Synopsys IncMississauga, Ontario, Canada 9d Lead the design and verification of next-generation SERDES PHY IP solutions and high-performance memory controller IPs for advanced semiconductor technologies.
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