Verification Engineer
Core
Develop SystemVerilog UVM and formal verification environments for block-level functional verification of CPU memory-system components.
Role type
Senior IC verification engineer (CPU microarchitecture)
Builds
High-quality CPU IP for next-generation Cortex-A processors
Domain
Semiconductor / CPU Design
Required skills
SystemVerilog, UVM, formal verification, RTL debugging, coverage closure, object-oriented programming, data structures, algorithms
Preferred skills
Cache coherence verification, virtual memory, address translation, out-of-order execution, register renaming, reservation stations, processor pipelines, reusable testbench design, functional coverage-driven methods
Technologies
SystemVerilog, UVM, simulation tools, formal verification tools
Responsibilities
Develop and debug verification environments for RTL designs; Create and maintain verification plans; Generate and run tests on logic simulation models; Define and implement functional and statistical coverage; Collaborate with design and architecture teams to resolve verification issues
Seniority
Senior, hands-on IC
