Staff Engineer - SerDes Verification
Core
Building UVM/SystemVerilog testbenches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams for high-speed SerDes interfaces.
Role type
Staff IC verification engineer (SerDes)
Builds
High-performance silicon for next-gen processors and AI systems
Domain
Semiconductor hardware design and verification
Required skills
UVM, SystemVerilog, formal verification, SerDes architectures, link training, equalization, signal integrity analysis, jitter/BER/eye diagram evaluation, protocol compliance (UCIe, PCIe, DDR, Ethernet, USB, DisplayPort), HDL (VHDL/Verilog), Python/Perl scripting, regression test automation
Preferred skills
DDR protocol verification (DDR3/4/5), UCIe protocol expertise, hardware description languages, fast-paced environment management
Technologies
UVM, SystemVerilog, VHDL, Verilog, Python, Perl, PCIe, UCIe, DDR, Ethernet, USB, DisplayPort
Responsibilities
Develop and execute verification plans and testbenches for SerDes IPs and subsystems; Drive formal verification by writing properties and assertions; Build directed and random verification tests; Perform simulations and debug timing, protocol errors, and design anomalies; Evaluate performance characteristics including jitter, BER, and signal integrity; Verify adherence to relevant SerDes protocols; Develop automated regression tests; Collaborate with design, hardware, and software teams to troubleshoot issues; Create detailed reports on verification results
Seniority
Staff, hands-on IC
