ASIC Design Verification Engineer - Slingshot
Core
Design Verification Engineer for HPE Slingshot interconnect ASICs used in HPC and AI systems, responsible for pre-silicon verification from test plan to sign-off.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Switch and NIC ASICs for future generation HPE Slingshot interconnects
Domain
Semiconductor / High-Performance Computing / AI Infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM/OVM, Testbench development, Scoreboard/Checker design, Functional coverage closure, Regression analysis, Bug triage, Scripting (Python/Perl/Tcl), EDA tools
Preferred skills
High-speed networking/NIC ASIC verification, Agentic AI tools for verification, Linux development environments, Distributed team collaboration
Technologies
SystemVerilog, UVM, OVM, Python, Perl, Tcl, EDA tools
Responsibilities
Develop SystemVerilog and UVM testbench components including bus functional models; Plan and implement block level scoreboards and checkers; Write and analyze functional coverage to drive closure; Triage regression failures and identify logic bugs; Apply scripting and AI-assisted tools to improve verification speed and quality; Provide guidance and mentoring to less experienced staff
Seniority
Senior, hands-on IC
