Sr. Staff Engineer - Design Formal Verification

Hyderabad, IndiaFull-time2026-10-30 → 2026-11-10

Core

Own and drive strategies to verify complex processor modules (instruction fetch, branch prediction, execution pipelines) using formal verification techniques.

Role type

Senior Staff Hardware Engineer (Design Formal Verification)

Builds

Verified processor designs for RISC-V compute platforms

Domain

Semiconductor / Chip Design / RISC-V

Required skills

Formal Verification, Formal Abstraction Techniques, Chisel, VHDL, Verilog, SystemVerilog, Assertion Libraries, Scripting/Automation, Debugging RTL

Preferred skills

Object-oriented Programming

Technologies

VC Formal, JasperGold, Chisel

Responsibilities

Identify blocks suitable for formal verification; Create formal test plans and sign-off metrics; Implement and maintain formal verification environments; Apply FV techniques to prove correctness; Debug RTL failure scenarios; Guide and train team members; Develop automation scripts; Review formal setups and proofs; Maintain assertion libraries

Seniority

Senior Staff, hands-on IC

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.