Emulation Engineer
Core
Define, develop, and execute pre-silicon test plans for chip architecture and micro-architecture using emulation platforms.
Role type
Senior IC emulation engineer (ASIC pre-silicon verification)
Builds
Sub-system and chip-level test plans, synthesizable models, and robust emulation environments
Domain
Semiconductor hardware design and verification (ASIC)
Required skills
Verilog/SystemVerilog, C/C++, Tcl, Python, emulation platform expertise, debugging, automation scripting
Preferred skills
Experience with Zebu/Palladium, speed bridges, high-speed interfaces (PCIe), DPI transactors, assertions, coverage-driven verification
Technologies
Palladium, Zebu, Tcl, ITcl, Python, C/C++, Verilog, SystemVerilog
Responsibilities
Conduct detailed studies of chip architecture to define pre-silicon test plans; Verify design and micro-architecture using emulation platforms; Develop sub-system and chip-level tests; Build and synthesize Verilog/SystemVerilog-based models; Perform block, sub-system, and chip/system-level debugging and root cause analysis; Develop and optimize automation scripts and emulation methodologies; Create reusable synthesizable design blocks, libraries, and verification components; Build and maintain robust emulation environments; Collaborate with Architecture, Design, DV, and FW/Validation teams
Seniority
Senior, hands-on IC
