DFT - SOC Lead
Core
Drive DFT architecture definitions for Scan, MBIST, PHY, high-speed IOs, communication controllers, and FPGA logics to ensure manufacturable solutions from early design to high-volume silicon production.
Role type
Senior DFT SOC Lead (IC)
Builds
Future AMD semiconductor products (processors, AI chips)
Domain
Semiconductor / Digital IC Design
Required skills
DFT architecture definition, Scan/Scan Compression, MBIST, ATPG, PHY design, high-speed IO, Verilog, synthesis, STA, verification methodology, post-silicon debug, FPGA logic, embedded design
Preferred skills
Tessent Streaming Scan Network (SSN), ATE environment, oscilloscope/logic analyzer usage
Technologies
Verilog, ATPG, Tessent SSN, FPGA, ATE tools
Responsibilities
Manage DFT activities across architecture, design implementation, verification, and test implementation; Drive internal DFT teams to create test solutions; Plan for diagnosability and yield improvement; Collaborate with design and physical design teams on DFT structures.
Seniority
Senior, hands-on IC with leadership
