Formal Verification Intern
Core
Formal verification of System-on-a-chip (SoC) design blocks and IPs to ensure bug-free functionality for Apple products.
Role type
Formal Verification Intern
Builds
High-quality functional SoC designs and IP blocks
Domain
Semiconductor hardware design and formal verification
Required skills
Digital design logic, formal verification techniques, temporal logic assertion languages (SVA/PSL), EDA formal tools, CAD tool development, scripting (TCL/PERL)
Preferred skills
CPU design knowledge, pipeline architectures, memory/DMA controllers, out-of-order execution, cache coherence, hardware specification interpretation
Technologies
SVA, PSL, EDA formal tools, TCL, PERL
Responsibilities
Create formal micro-architecture specifications, develop formal verification test plans, prove design properties and find bugs, architect novel verification solutions, develop reusable formal models and verification code
Seniority
Intern
