Video Design Verification Sr Engineer
Core
Design and verify video pipeline hardware systems, including digital/analog/RF/optical components and Tensilica DSPs, using coverage-driven verification methodologies.
Role type
Senior IC hardware verification engineer (video pipeline)
Builds
Next-generation mobile and IoT chips with integrated video processing capabilities
Domain
Semiconductor hardware engineering, video processing, digital signal processing
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, C-based reference modeling, failure debugging (Verdi), assertion development, gate-level simulation, power-aware simulation, formal verification, emulation, scripting (Perl, Python), Tensilica architecture knowledge
Preferred skills
Video pipeline domain expertise, sub-system verification experience
Technologies
System Verilog, UVM, Verdi, VCS, IUS, Tensilica, C, Perl, Python
Responsibilities
Develop coverage-driven testbenches with stimulus, agents, monitors, and checkers; debug failures using Verdi and log files; create assertions and C-based reference models; perform gate-level, power-aware, formal, and emulation simulations; collaborate with designers to meet performance requirements
Seniority
Senior, hands-on IC
