Senior Staff Engineer, Design Verification (Power & Analog IC's)
Core
Architect and implement verification environments for complex SoC designs in next-generation Power management solutions, driving block-level, subsystem-level, and full-chip verification.
Role type
Senior Staff IC Design Verification Engineer (Power & Analog)
Builds
Verification environments, agents, sequences, drivers, monitors, and scoreboards for Power management SoCs
Domain
Semiconductor / Power Management ICs / SoC Design
Required skills
UVM methodology, Verilog/SystemVerilog, C/C++, Perl/Python scripting, Gate-level simulation, Coverage analysis, Debugging RTL/Gate, SoC architecture knowledge, Mixed-signal design understanding, Analog components knowledge (ADC, DAC, PLL, Oscillators, PI controllers), Regression systems, Revision control
Preferred skills
Experience with industry-standard simulators, ATE vector bring up, Test pattern conversion, Mentorship of junior engineers
Technologies
UVM, Verilog, SystemVerilog, C, C++, Perl, Python, Shell, Gate-level simulators, Regression systems, Revision control systems
Responsibilities
Define and own verification plans, methodologies, and coverage strategies; Architect and implement verification environments from scratch; Lead end-to-end verification including gate-level simulations, debugs, and coverage closure; Mentor junior and mid-level verification engineers; Integrate industry-standard VIPs and create custom transactors; Convert verification tests to test patterns and assist Test Engineers on ATE vector bring up.
Seniority
Senior Staff, hands-on IC
