Staff Engineer Design
Core
Validate next-generation WLAN MAC designs for cutting-edge wireless products using industry-leading verification methodologies.
Role type
Staff IC digital verification engineer (WLAN MAC)
Builds
Next-generation WLAN MAC digital designs and subsystems
Domain
Semiconductor / Wireless Communications
Required skills
SystemVerilog, UVM, WLAN MAC verification, wireless communication protocols, AXI/PCIe bus protocols, CDC/RDC analysis, EDA tools (Synopsys/Cadence/Siemens), regression management, debug simulation
Preferred skills
802.11ax/802.11be standards knowledge, Verification IP (VIP) development, gate-level verification sign-off
Technologies
SystemVerilog, UVM, AXI, AHB, APB, PCIe, Synopsys, Cadence, Siemens EDA
Responsibilities
Develop and execute comprehensive verification plans for WLAN MAC digital designs; Build and maintain System Verilog/UVM-based verification environments; Create test plans and functional tests for WLAN MAC protocols; Develop and integrate Verification IP (VIP) for industry-standard interfaces; Drive functional, assertion, and code coverage closure; Perform regression management and debug simulation failures; Conduct CDC/RDC analysis and support gate-level verification sign-off
Seniority
Senior, hands-on IC
